Fix CMIS and preemphasis lane mapping issues #508
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jemifdo
commented
Jul 3, 2024
jemifdo
commented
- CMIS port db is updated dynamically on DPB
- check_datapath_init_pending is disabled as it need to be done for different lanes sequentially instead of concurrent
- Preemphasis to lane map now works when not all lanes of the port are used
- get_physical_to_logical is now sorted to generated the correct preemphasis values
- CMIS port db is updated dynamically on DPB - check_datapath_init_pending is disabled as it need to be done for different lanes sequentially instead of concurrent - Preemphasis to lane map now works when not all lanes of the port are used - get_physical_to_logical is now sorted to generated the correct preemphasis values - Add API to support the selection of the preemphasis key in a platform vendor dictated way instead of generic one
prgeor
requested changes
Jul 5, 2024
|
@prgeor I mean the case where 1x100G breakout mode is used in an 8 lane port (with speed 25G per lane) and for this the preemphasis dict must have values only the first four lanes. Remaining 4 lanes are unused by the port. |
'subport' is now part of the PORT config, so does not require any derivation
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